Integrated circuit fabrication on semiconductor structures for ULSI (ultra large scale integration) require multilevels of metal interconnections for electrically interconnecting the discrete semiconductor devices on the semiconductor chips. Typically the insulating layers between the metal interconnections is silicon oxide (SiO.sub.2) having a dielectric constant from about 4.1 to 4.5 (air having the lowest dielectric constant of 1.0). However as the device dimensions decrease, the spacing between the devices decrease to further miniaturization and the intra-level and inter-level capacitances (C) undesirably increase between the metal lines when using an insulating layer, e.g. SiO.sub.2, having the same dielectric constant because the capacitance C is inversely proportional to the spacing between the metal lines (and is directly proportional to the dielectric constant k)
So insulating materials having lower dielectric constants k are needed to reduce the capacitance C, and thus reduce the RC (resistance.times.capacitance) time delay, so as to increase the performance of the circuit (frequency response) since the signal propagation time in the circuit is adversely affected by the RC time delay. One way to minimize RC time delays is, as noted above, using an insulating material having a lower dielectric constant k will also reduce RC time delays by decreasing capacitance C. One such inorganic low k material that is used is fluorine-doped silicon oxide, also known as fluorinated oxide or fluorine silicon glass (FSG). Also, using a good electrical conductor for the metal interconnections, such as using copper (Cu), instead of aluminum (Al) will reduce the resistance R. Once such a metal, e.g. Cu,--FSG metal interconnection structure is formed, the surface is covered by a dielectric cap, for example SiN.
Currently, chemical vapor deposition (CVD) of FSG is used for sub-quarter micron processes and chemical mechanical polishing (CMP) is the dominant process for copper (Cu) damascene. However, water in Cu CMP slurries, photo resist strip, or in subsequent cleaning solutions attack the surface of the FSG (Si--F bonds) forming undesired silanol (Si--OH) and affecting bonding between the SiN dielectric cap layer and the FSG resulting in peeling of dielectric layers. Bubbles are found at the FSG/SiN interface after SiN deposition 1 hour of 400.degree. C. alloy.
Also, during the FSG integrated process, some H bond will exist in the FSG film (possibly from water or other film that diffused to the FSG film) which may react with unstable fluorine (F) in the FSG film to form HF which will attack the metal film to form FSG bubbles.
U.S. Pat. No. 5,759,906 to Lou describes an FSG intermetal dielectric layer and a method for fabricating a planar intermetal dielectric using a non-polish back technology to provide a planar multilevel metal structure. One embodiment uses low k materials, e.g. an FSG layer covering layers of FLARE.TM., to reduce the RC time delays for the interconnecting levels of metal.
U.S. Pat. No. 5,420,069 to Joshi et al. describes a Cu/Cu.sub.x Ge.sub.y alloy or Cu/Cu.sub.3 Ge (copper/copper-germanium) phase bilayer interconnect metal lines layer to prevent electomigration and dissimilar metals like Al--Cu may be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electomigration performance. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects are a problem are allowed by the Cu/Cu.sub.x Ge.sub.y alloy or Cu/Cu.sub.3 Ge phase bilayer.
U.S. Pat. No. 5,891,513 to Dubin et al. describes a Cu interconnect with a Ta (tantalum) barrier layer and a SiN cap dielectric barrier layer and a method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer.
U.S. Pat. No. 5,395,796 to Haskell et al. describes a silicon-oxyfluoride polymer and sputtering process for an intermetal dielectric (IMD) layer. An etch stop layer for permitting distinguishing between two similar layers, such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer and permits closer placement of metal conductor surfaces.
U.S. Pat. No. 5,763,010 to Guo et al. describes a method of stabilizing a halogen-doped silicon oxide film to reduce halogen atoms migrating from the film during subsequent processing steps by subjecting the deposited halogen-doped silicon oxide film to a degassing step by briefly heating to a temperature between about 300 and 550.degree. C. before deposition of a diffusion barrier layer. In the preferred embodiment the halogen-doped silicon oxide film is an FSG film that is degassed for between about 35 and 50 seconds.
The "Pursuing the Perfect Low-k Dielectric," Semiconductor International, September 1998, pp 64-74, article to Peters, discusses low-k dielectrics such as hydrogen silsequioxane (HSQ), fluorinated oxides (including FSG), silicon-based spin-on polymers, SiLK, FLARE, VELOX, BCB and organic and inorganic CVD films.
The "Improvement of Adhesion Properties of Fluorinated Silica Glass Films by Nitrous Oxide Plasma Treatment," J. Electrochem. Soc., Vol. 144, No. 7, July 1997, pp 2559-2564, article to Swope et al., describes the effects of nitrous oxide (N.sub.2 O) plasma surface treatment of FSG films in improving film stability an adhesion properties. Highly doped FSG films had to adhesion problems when the subsequent depositions occurred shortly after FSG deposition and plasma treatment, however all films blistered after being exposed to air for 2 days before passivation deposition. No evidence was developed that the moisture resistance of these FSG films was substantially improved by the N.sub.2 O plasma treatment.
The "Stability of Si--O--F low-k dielectrics: Attack by water molecules as function of near-neighbor Si--F bonding arrangements," J. Vacuum Sci. Technol., A 16(3), May/June 1998, pp 1525-1527, article to Yang, et al. describes the stability of Si--O--F alloy films with respect to attack of Si--F bonds by water molecules. Their calculations show that the reaction: EQU H.sub.2 O+2Si--F.fwdarw.2HF+Si--O--F
is exothermic by about 0.7 eV. The reaction energetics is a function of the distance between the F atoms of the Si--F groups and the H atoms of the H.sub.2 O molecule. Strong hydrogen bonding between H and F atoms is found. An upper limit for chemically stable F corporation has been determined to be about 10-12 at. % F, which corresponds to static dielectric constant of 3.2-3.4.
U.S. Pat. No. 5,858,869 to Chen et al. describes a method for making multilevel electrical interconnections having a planar intermetal dielectric (IMD) with low dielectric constant k and good thermal conductivity. Metal lines are formed on which anisotropic plasma oxide (APO) is deposited resulting in a thin oxide on the sidewalls of the metal lines and a much thicker oxide on top of the lines. The APO provides wider openings between metal lines filled with a low k dielectric polymer thereby reducing the RC (resistance.times.capacitance) time delay of the circuit. FSG is used to provide a lower dielectric constant k for further reducing the RC delay and a better thermal conductivity constant K for minimizing the Joule heating when the circuit is powered up.
U.S. Pat. No. 5,876,798 to Vassiliev describes films of fluorinated silicon oxide having no surface damage and good step coverage with no trapped voids, suitable for use as intermetal dielectrics, deposited in the first embodiment by means of chemical vapor deposition (CVD) at reduced pressure using fluorotriethoxysilane (FTES) and tetra-exthyloxysilane (TEOS) as the precursors, together with ozone (mixed with oxygen). In a second embodiment, the TEOS is omitted and in a third embodiment a stacked layer is formed.
U.S. Pat. No. 5,407,529 to Homma describes a pattern formation method that used a tri-level resist structure with a fluorine contained SiO.sub.2 intermediate film.
U.S. Pat. No. 5,866,945 to Chen et al. describes a spin-on hydrogen silsequioxane (HSQ) (replacing spun-on glass (SOG)) employed to gap fill metal layers in manufacturing a high density, multi-level layer semiconductor device. The degradation of deposited HSQ layers during formation of borderless vias is overcome by treating the degraded HSQ layer with an H.sub.2 containing plasma to restore the Si--H bonds, thereby passivating the surface and preventing moisture absorption, before filling the via opening with conductive material, such a barrier layer.
U.S. Pat. No. 5,571,734 to Tseng et al. describes a method of fabricating a dielectric having an increased device current drive. A nitrogen-containing dielectric is formed then a fluorine-containing specie is introduced into a gate electrode overlying the nitrogen-containing dielectric. The fluorine is then driven up into the underlying nitrogen-containing dielectric. The interaction between the fluorine and nitrogen increases the overall current drive.